The many ‘modes’ of multimode

Fiber types are differentiated as multimode or single mode. Single mode was always easy for me to understand but I could never quite understand what ‘multimode’ actually meant. I’m written some notes for myself on this topic that I thought I’d share. I’m sure some physicists will have an allergic reaction to my take, but I’m happy to pay that price to learn a little more.

Continue reading

Packet pushers podcast – Hardware Resources

It’s been quite a while since I’ve posted here but I wanted to highlight some work I’ve been doing with Greg Ferro and Simon Chatterjee on the Packet Pushers podcast. We recorded a three part series where we dive deep into the guts of networking hardware. All three shows are now published on the packet pushers podcast.

Show 186 – The Silicon Inside Your Network Device – Part 1

Show 187 – The Silicon Inside Your Network Device – Part 2

Show 190 – The Silicon Inside Your Network Device – Part 3

If you’re just arriving here from the Packet Pushers site, I’ve put together a dedicated page to capture all of my hardware-related posts.

The Network Sherpa – Hardware page 

Enjoy!

Is CPU or ASIC responsible for forwarding?

I received the question below from reader Ned as a comment on my 24-port ASIC post and thought that the discussion was worth a post of it’s own.

…Would you be able to speak a bit about the actual physical path or packet flow a packet takes inside the switch itself and how does the hardware forwarding take place within the switch and asic. When does packet get sent to the Asic. Is it happen on ingress or on egress? When does packet get analyzed by CPU or control plane. If the CPU never sees the actual packet how does asic know where to forward the packet and does that mean the packets stay within asic itself and is that what is meant to be hardware forwarding. Is Asic = dataplane. Tx

I like this question because it captures a lot of my early assumptions and concerns about data and control plane separation. My response assumes a single-stage modern switch-on-chip ASIC without backplane or fabric.  Continue reading

Hardware – What’s the ‘holdup’?

iStock_000001593430SmallThis post discusses power supply ‘holdup’, and how it can impact network or server hardware uptime. The holdup time or ‘output holdup time’ is the length of time that a given power supply can maintain output power to the switch or server after it’s input power supply has been cut. The dependent host will shut down if the power supply isn’t restored to the PSU before the hold-up time expires. I like to think of holdup time as a power buffer.

Continue reading

Hardware – Equalization and Pre-emphasis

Screen Shot 2014-02-09 at 9.39.58 AMBefore we look at equalization and pre-emphasis, we should examine some fundamentals of waves and signals. A perfect square wave is a really useful way of representing a waveform in the time-domain, but it’s not the only way of looking at the signal.The name ‘time-domain’ may be new but the view is familiar to us all, you have amplitude on the vertical axis and time you have time on the horizontal scale.

Ideal square waves need infinite bandwidth

The square wave is easy to understand, but unfortunately the ‘perfect’ square wave is a purely theoretical construct. A square wave is actually constructed of many sine waves of different frequencies and amplitudes added together [1]. The fundamental frequency of the signal (e.g. 10Khz) is a sine wave and has the highest amplitude. However there are other many other frequencies called harmonics, which must be successfully received and added to the fundamental signal to ‘square out’ the waveform. To view these signals we need to switch to a new view, the ‘frequency-domain’.  Continue reading

Hardware – Comparing 10G SFP+ with XFP

320px-SFP-side

By Adamantios (Own work) [GFDL (http://www.gnu.org/copyleft/fdl.html), CC-BY-SA-3.0 (http://creativecommons.org/licenses/by-sa/3.0/)

In the last post I discussed clock and data recovery (CDR). This post examines an application of re-timers (or CDRs) within XFP and SFP+ transceivers. I’ve previously covered the size, power and connector differences of 10G transceivers before, but this post will focus on the differences between XFP and SFP+ and how they connect to the ASIC.

Take a look at the XFP block digram below which shows the XFI electrical interface from an XFP module connecting to the the host device (ASIC or PHY chip) on left. The test-points (arrows marked A,B,B’,C,C’ & D) aren’t part of the physical interface but are markers that we can use to discuss the diagram. The four boxes on the right represent transmit and receive sub-assemblies, drivers and amps. You’ll find similar functional blocks in all optical transceivers.

Continue reading