Is CPU or ASIC responsible for forwarding?

I received the question below from reader Ned as a comment on my 24-port ASIC post and thought that the discussion was worth a post of it’s own.

…Would you be able to speak a bit about the actual physical path or packet flow a packet takes inside the switch itself and how does the hardware forwarding take place within the switch and asic. When does packet get sent to the Asic. Is it happen on ingress or on egress? When does packet get analyzed by CPU or control plane. If the CPU never sees the actual packet how does asic know where to forward the packet and does that mean the packets stay within asic itself and is that what is meant to be hardware forwarding. Is Asic = dataplane. Tx

I like this question because it captures a lot of my early assumptions and concerns about data and control plane separation. My response assumes a single-stage modern switch-on-chip ASIC without backplane or fabric.  Continue reading

My 10G switch goes up to 11

Stealing bits

Nailing down the true speed of a 10GbE link can be tricky. For a start you to define ‘speed’ and ‘capacity’. Ivan Pepelnjak offers a nice summary in this post. Then there are little surprises. A former colleague of mine Fred Westermark first introduced me to the Ethernet interframe gap. I had never heard of this before and felt a bit cheated to be honest.  Since when do ‘bits’ need a rest. Pfff.

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