In the last post I discussed clock and data recovery (CDR). This post examines an application of re-timers (or CDRs) within XFP and SFP+ transceivers. I’ve previously covered the size, power and connector differences of 10G transceivers before, but this post will focus on the differences between XFP and SFP+ and how they connect to the ASIC.
Take a look at the XFP block digram below which shows the XFI electrical interface from an XFP module connecting to the the host device (ASIC or PHY chip) on left. The test-points (arrows marked A,B,B’,C,C’ & D) aren’t part of the physical interface but are markers that we can use to discuss the diagram. The four boxes on the right represent transmit and receive sub-assemblies, drivers and amps. You’ll find similar functional blocks in all optical transceivers.
Focus on the CDR (re-timer) blocks to the left of the XFP module. The first thing to note is that there are two re-timers, one for the transmit path and one for receive. The Receive Optical Sub Assembly (ROSA) translates the optical signal received from the fiber into an electrical signal. The signal is then boosted by the Post Amp, before being re-timed by the CDR block. The CDR block is acting solely as a re-timer here, reconditioning the signal received from the ROSA. The CDR re-transmits this signal using the XFI serial interface to the ASIC. Similarly the CDR on the XFP’s transmit path, receives a degraded signal from the ASIC and applies re-timing to prepare the electrical signal for optical conversion by the the Transmit Optical Sub Assembly (TOSA).
At the bottom of the diagram you’ll see the PMD, PMA and PCS markers showing you which PHY-layer sub-functions are mapped to each block. You should note that XFI is a ‘just’ a set of electrical requirements and tolerances expressed as compliance masks in the XFP MSA Specification. The serial bit stream sent on the XFI interface is exactly the same 64b/66b encoded bit stream received on the wire. XFI isn’t ‘intelligent’ and the IEEE may no reference to XFI nor the SFI interface shown below.
SFP+ transceivers are cheaper, smaller and less power-hungry than XFP modules, and performs similar duties. How is this possible? The XFP MSA specification was agreed many years before SFP+, so Moores Law would definitely have helped to shrink the internal circuitry.
However the main reason for the size, power and cost improvements over XFP is that the SFP+ simply removes the CDR blocks from the module. Tada!! In a classic case of lazy engineering the SFP+ module makes the signal conditioning the responsibility of the upstream ASIC or signal conditioning chip.
The SFI interface almost identical to the XFI interface you saw in the first diagram. If you zoom into the PMA block now you’ll see that it has two new sub-functions. The signal conditioning responsibility has shifted from the SFP+ module to the device performing the PMA function. On the TX side, the signal needs pre-emphasis to prepare it for the transmission to the SFP+ module. On the RX side the signal needs serious clean-up as it now contains noise and jitter from the circuit and the optical channel.
The SFP+ module performs less functions than the XFP module. The CDR blocks which were included in XFP module are discarded by the SFP+ which shifts the responsibility of signal conditioning to other components on the circuit board. The PMA sub-layer must take up the signal conditioning role, but needs to adopt different techniques as it working at the other end of the noisy circuit-board.
Pre-emphasis and Equalization are the tools employed at the PMA and they will be the subject of the next hardware post.
The diagrams and much of the information in this post have gleaned from the fantastic 40GEthernet Blog. I’ve given you my simplified take on this, but please visit the authors blog if you want a deeper and more precise explanation on SFP+, 40G and more.