Using IPMI Serial-over-LAN for server consoles

I’ve been trying to learn linux networking and virtualisation using a donated server in a remote lab. The server didn’t have an IP-KVM attached but it did have a working IPMI connection. Not that I’d need it of course; I was experimenting with network settings whilst ssh’d into a server that was four and a half thousand miles away. What’s the worst that could happen?

Of course the inevitable happened and I haplessly disabled my eth0 interface. I was locked out of the server, but was happy to learn that the Intelligent Platform Management Interface (IPMI) was a powerful tool indeed.

Both the IPMI protocol and HP’s iLO allow you to connect to the Baseboard Management Controller (BMC) on high-end servers. The BMC is a micro-controller embedded on the server motherboard which allows remote management without relying upon the server OS. The two specific functions I would need were the ability to remotely reset the server, and a view of the server console. Continue reading

Is CPU or ASIC responsible for forwarding?

I received the question below from reader Ned as a comment on my 24-port ASIC post and thought that the discussion was worth a post of it’s own.

…Would you be able to speak a bit about the actual physical path or packet flow a packet takes inside the switch itself and how does the hardware forwarding take place within the switch and asic. When does packet get sent to the Asic. Is it happen on ingress or on egress? When does packet get analyzed by CPU or control plane. If the CPU never sees the actual packet how does asic know where to forward the packet and does that mean the packets stay within asic itself and is that what is meant to be hardware forwarding. Is Asic = dataplane. Tx

I like this question because it captures a lot of my early assumptions and concerns about data and control plane separation. My response assumes a single-stage modern switch-on-chip ASIC without backplane or fabric.  Continue reading

Hardware – What’s the ‘holdup’?

iStock_000001593430SmallThis post discusses power supply ‘holdup’, and how it can impact network or server hardware uptime. The holdup time or ‘output holdup time’ is the length of time that a given power supply can maintain output power to the switch or server after it’s input power supply has been cut. The dependent host will shut down if the power supply isn’t restored to the PSU before the hold-up time expires. I like to think of holdup time as a power buffer.

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Planning projects instead of burning benjamins

iStock_000007817002SmallEngineers are often unstuck by poor planning and get hit with large financial penalties as a result. Projects can become mired in delays and complications due to unforeseen costs and expenses. There are some unavoidable bumps in the road, but most could be foreseen and eliminated in advance. I want to share a few tips based on some experiences I’ve had over the years. Continue reading

Hardware – Equalization and Pre-emphasis

Screen Shot 2014-02-09 at 9.39.58 AMBefore we look at equalization and pre-emphasis, we should examine some fundamentals of waves and signals. A perfect square wave is a really useful way of representing a waveform in the time-domain, but it’s not the only way of looking at the signal.The name ‘time-domain’ may be new but the view is familiar to us all, you have amplitude on the vertical axis and time you have time on the horizontal scale.

Ideal square waves need infinite bandwidth

The square wave is easy to understand, but unfortunately the ‘perfect’ square wave is a purely theoretical construct. A square wave is actually constructed of many sine waves of different frequencies and amplitudes added together [1]. The fundamental frequency of the signal (e.g. 10Khz) is a sine wave and has the highest amplitude. However there are other many other frequencies called harmonics, which must be successfully received and added to the fundamental signal to ‘square out’ the waveform. To view these signals we need to switch to a new view, the ‘frequency-domain’.  Continue reading

Hardware – Is SFP+ just a smaller version of XFP?

320px-SFP-side

By Adamantios (Own work) [GFDL (http://www.gnu.org/copyleft/fdl.html), CC-BY-SA-3.0 (http://creativecommons.org/licenses/by-sa/3.0/)

In the last post I discussed clock and data recovery (CDR). This post examines an application of re-timers (or CDRs) within XFP and SFP+ transceivers. I’ve previously covered the size, power and connector differences of 10G transceivers before, but this post will focus on the differences between XFP and SFP+ and how they connect to the ASIC.

Take a look at the XFP block digram below which shows the XFI electrical interface from an XFP module connecting to the the host device (ASIC or PHY chip) on left. The test-points (arrows marked A,B,B’,C,C’ & D) aren’t part of the physical interface but are markers that we can use to discuss the diagram. The four boxes on the right represent transmit and receive sub-assemblies, drivers and amps. You’ll find similar functional blocks in all optical transceivers.

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