Hardware – Comparing 10G SFP+ with XFP


By Adamantios (Own work) [GFDL (http://www.gnu.org/copyleft/fdl.html), CC-BY-SA-3.0 (http://creativecommons.org/licenses/by-sa/3.0/)

In the last post I discussed clock and data recovery (CDR). This post examines an application of re-timers (or CDRs) within XFP and SFP+ transceivers. I’ve previously covered the size, power and connector differences of 10G transceivers before, but this post will focus on the differences between XFP and SFP+ and how they connect to the ASIC.

Take a look at the XFP block digram below which shows the XFI electrical interface from an XFP module connecting to the the host device (ASIC or PHY chip) on left. The test-points (arrows marked A,B,B’,C,C’ & D) aren’t part of the physical interface but are markers that we can use to discuss the diagram. The four boxes on the right represent transmit and receive sub-assemblies, drivers and amps. You’ll find similar functional blocks in all optical transceivers.

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Hardware – Clock and Data Recovery

Clock and data recovery is an essential physical-layer function of modern switch and router hardware. Digging deep into the electronics of a router may not be your thing, but clock recovery is a fundamental building block for other network hardware functions. For example, serial to parallel data conversions require reliable clock and data recovery (CDR) to function effectively. It’s hard to understand serial to parallel conversions or signal conditioning without learning about CDR first.

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